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Power consumption is the biggest technical challenge facing chip makers today as they try to cram computer-level electronics into tiny smartphones and other mobile devices. But SuVolta plans to alleviate some of that burden with a new technology that reduces power consumption by up to 50 percent.
The Los Gatos, Calif.-based company has been talking about this semiconductor capability for 18 months and today it announced that its Deeply Depleted Channel technology has been proven in factories at Fujitsu Semiconductor, a major Japanese chip manufacturer. SuVolta said it plans to have the technology commercially available in the first half of 2013.
SuVolta and Fujitsu Semiconductor will talk about the development at the International Electronic Devices Meeting in San Francisco tomorrow.
The technology reduces power consumption without impacting a chip’s performance. The result is that chip makers will be able to reduce the power supply voltage and transistor sizes to smaller dimensions below 20 nanometers. (A nanometer is a billionth of a meter).
The company says its PowerShrink technology addresses a fundamental problem in the physics behind transistors, the basic building blocks of all electronic chips. If it works, the technology could help improve battery life in portable products — smartphones, tablets, and notebooks — and offer an alternative to a revolutionary Intel technology known as Tri-Gate.
SuVolta attacks a problem called transistor variation. It minimizes the electrical variation in each of the millions of transistors on a chip. On the manufacturing level, SuVolta merely tweaks the “recipe” for making a chip. The result is that it reduces the variation in voltage for a chip, allowing for efficiency improvements.
“The IEDM paper results confirm that Fujitsu Semiconductor’s DDC-enabled process offers the best combination of performance and reduced power consumption of any 65 nanometer or 55 nanometer process,” said Haruyoshi Yagi, corporate senior executive vice president at Fujitsu Semiconductor Limited. “The integration of the DDC technology into Fujitsu Semiconductor’s low-power process has met all of our expectations. The DDC-based technology is expected to be commercially available in the first half of 2013 in a 55 nanometer process offering.”
Fujitsu Semiconductor is SuVolta’s first licensee for the technology.
“We are extremely pleased that parts built with Fujitsu Semiconductor’s DDC-based 55nm process will soon be available,” said Bruce McWilliams, president and CEO at SuVolta, Inc. “By enabling significant performance increases and up to 50 percent power reduction, SuVolta is providing the industry with a flexible and cost-effective device technology option, extending the benefits of CMOS technology.”
SuVolta has funding from Kleiner Perkins Caufield & Byers, August Capital, NEA, Bright Capital, Northgate Capital and DAG Ventures.