It isn’t easy to establish a custom chip architecture these days. But Tilera has managed to do that in the past year and now it is moving on to its second generation of products.
Today, San Jose, Calif.-based Tilera is launching two models of its new TilePro family of chips for telecom and networking infrastructure where energy-efficient performance is paramount. The chips are based on the custom Tile architecture that Tilera debuted a year ago.
If Tilera succeeds, it will be able to establish an alternative processor platform for communications customers. It will also prove that the day of launching new chip architectures isn’t dead, suggesting that there is still room for innovative chip design in a decades-old industry as new computing problems and applications surface.
Each chip has either 36 or 64 tiles (processing cores). They’re connected via a unique communications structure known as a mesh. Anant Agarwal, an MIT professor who is chief technology officer, said that the mesh allows the tiles to maximize processing performance without running into the typical communications bottlenecks that other chips face.
As an example, a tile can process a piece of data and deliver the result to the next tile, which can start using that data right away. Other processors can do that, but not during the same tick of the clock. This makes the chips faster and it allows them to scale. That is, you can add lots of tiles to a chip and its performance will keep on improving. With other chips, the bottlenecks are so severe that 48 cores might not be any more powerful than 32.
“Over time, there have been fewer and fewer chip architectures in the market,” Agarwal said. “To launch a new one, you have to do something disruptive.” Read the rest of this entry »
