For 50 years, Moore’s Law has reliably described exponential advances in silicon speed, power and functionality. But with the cost per transistor rising for the first time in history, we’ve entered an era of diminishing returns.

We need to get smarter about hardware and software innovation in order to get the most value from the emerging Internet of Things. And perhaps the smart thing to do is to hit “pause” on the half-century race to cram ever more transistors onto a single slice of silicon.

If we are to achieve the vision of connecting tens of billions of devices to the Internet — Cisco predicts 40 billion smart objects and another 10 billion traditional devices and machines with embedded smarts — we’re going to need a huge supply of low-cost chips with communications capabilities. The good news is that innovation and growth can continue at the same pace but only if we take a break from the relentless pressure of doubling the transistor count every two years.

To date we’ve kept pace with Moore’s Law by shrinking chip features, or nodes, to ever-smaller, nanoscale dimensions. (How big is a nanometer? It’s about as long as your fingernail grows in one second. Slice a human hair lengthwise about 100,000 times, and that’s a nanometer.) The cost-effectiveness ratio seems to have hit the sweet spot at about 28 nanometers. Each incremental advance beyond that has required ever-greater investments, reducing the bang-per-buck calculus.

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The cost per transistor is rising for the first time since Moore stated his observation. With 28nm as a ‘sweet spot’, the time has come to look at ways to add more to Moore for the next generation of innovation.

Above: The cost per transistor is rising for the first time since Moore stated his observation. With 28nm as a ‘sweet spot’, the time has come to look at ways to add more to Moore for the next generation of innovation.

Chips will continue to shrink, of course. We, along with other semiconductor companies are continuing to push toward the next goal of 10nm, but going beyond 10nm will require the development of new technologies, materials, and manufacturing processes that are still being perfected. Extreme Ultraviolet (EUV) lithography, exotic semiconductor materials, multiple 3D chip-stacking and 450mm wafers are just a few of the new, breathtakingly expensive avenues of research.

However, there are many levers we can pull with 28nm silicon to propel the industry forward and enable the Internet of Things era of innovation and growth from literally thousands of developers. We can drive cost, size, and power-efficiency improvements through better design engineering versus better process engineering. IoT devices typically have much smaller transistor counts and therefore don’t require the latest (and most expensive) process nodes.

Adhering to the premise that 28nm is the optimum node size, then solidifying that node as the platform of choice and integrating more functionality, such as analog and RF components, is the next logical step. Analog components don’t “scale” as well as digital components, but integrating them into relatively mature 28nm platforms will accelerate the connection of everything from watches, personal healthcare, and home appliances to automotive, transportation, agriculture, manufacturing, and industrial controls.

As an industry, we have access to low-cost hardware, from sensors to signal conditioners and wireless interfaces. Innovators are developing the ideas and bringing them to life in amazing new applications. All we, as an industry, need to do now is focus on standardizing the interfaces to ensure interoperability — and stand out of the way. Even with Moore’s Law on pause, the best days of the semiconductor industry are yet ahead.

Henry Samueli is CTO and cofounder of Broadcom and serves as Chairman of the Board. In this role, he is responsible for driving the vision of Broadcom’s research and development activities as well as helping to lead corporate-wide engineering development strategies.