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At the Los Altos home of Intel cofounder Robert Noyce, company executives, architects, and fellows revealed their plans to expand Intel’s processors and other chips into new markets.

During “Architecture Day” on Tuesday, the team said it anticipates the next decade will see more changes in computing architecture than we’ve seen in the past 50 years. Intel believes this will create new addressable market opportunities worth more than $300 billion by 2022.

Part of the point of the event was to show how Intel got its groove back. I must admit, I found the array of activity and the depth of the presentations to be impressive. It was a reminder of the potential of a company that generated $63 billion in revenues last year and anticipates $71.2 billion this year.

Above: Bob Noyce’s home in Los Altos, California.

Image Credit: Dean Takahashi

Intel is focusing on next-generation chip architectures — the foundations for many families of chips — that will handle data-intensive workloads for PCs and other smart consumer devices, high-speed networks, ubiquitous artificial intelligence (AI), specialized cloud datacenters, and autonomous vehicles.


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The company can’t do everything, and executives were candid about the need to focus on getting Intel to innovate again, rather than eking out 5-percent-per-year performance improvements.

“We have starved you for information for three years, and now we have food,” said Raja Koduri, chief architect and senior vice president at Intel, as he opened talks in the room where Intel’s first board meetings took place in the 1960s.

Making Intel great again

Above: Raja Koduri is chief architect and senior vice president at Intel.

Image Credit: Dean Takahashi

As Koduri exited AMD and thought about what to do next, he realized he wanted to go to a place that was ambitious, open to transformation, and capable of operating at the largest scale. Intel fit the bill, in part because it needed to change.

Intel is eager to show it has recovered from a bad manufacturing misstep that caused it to fall off the regular cadence of manufacturing improvements. And so on Tuesday the company demoed a range of chips that were made with its new 10 nanometer (where the width between circuits is only 10 billionths of a meter wide) manufacturing process.

The aforementioned delay in moving to a new manufacturing technology was accompanied by the renewed competitiveness of Advanced Micro Devices, which has captured a higher share of the processor market with its Zen processor architecture.

With the slowing of Moore’s Law (the famous prediction in 1965 made by Intel chairman emeritus Gordon Moore that the number of transistors on a chip will double every year), the design and architecture of processors will have to dramatically improve if the coming years are to bring the same pace of technological improvement as we’ve seen in the past 50 years. Intel’s recent slip has made people wonder if Moore’s Law, limited by laws of physics for very small devices, is coming to an end.

“We do not want to let that happen ever again,” Koduri said in a small press group Q&A. “When something bad happens, the whole pipeline clogs. We are working on it. It’s a challenge, and something we are focused on.” The challenge has to do with ensuring proper coordination between manufacturing and design and making adjustments when one of these falls off schedule.

A confluence of such issues slowed Intel’s growth and may have contributed to the board’s decision to part ways with former CEO Brian Krzanich in June. Bob Swan, former chief financial officer, has been acting CEO since then, with no permanent CEO named yet. And Intel is in a tough competitive spot when it comes to dealing with rivals like AMD, Nvidia, Apple, Samsung, TSMC, and Qualcomm. The ghost of Bob Noyce, which you could say seemed pretty real in his former home, would not be happy with this Intel.

At stake is leadership in the $450 billion semiconductor industry, and the pole position in defining the future of computing. Koduri and crew plan to design their way out of this problem.

“People are saying Moore’s Law is dead,” Koduri said. “We call this the Architecture Era. We are going to architect our way around the slopes in this era.”

A team with outside perspectives

Above: Jim Keller is a rock star among chip architects. He is a senior vice president at Intel.

Image Credit: Dean Takahashi

Koduri, the former graphics chief at rival Advanced Micro Devices, and Venkata “Murthy” Renduchintala, group president at Intel and the highest-ranking executive at the event, both acknowledged the competitive pressure on the company.

But Intel has been willing to bring in outsiders to help guide its tens of thousands of chip designers. Renduchintala joined Intel in 2015 after leaving one of the top executive posts at rival Qualcomm. Koduri left AMD after a sabbatical in 2017, and he joined Intel as its chief architect in November 2017. Jim Keller, another chip design legend and architect of AMD’s comeback with the Zen processors, joined Intel in April after leaving Tesla.

This new set of voices helped challenge Intel’s internally grown thinking about computer architectures, said Renduchintala. Rather than upset the apple cart or remake everything, these outside views are helping challenge and test the design team’s assumptions about where to go, he said.

“I came from the outside. Are we losing leadership on our key pillars?,” Koduri asked. “What are the essential ingredients we need for our aspiration? What are the key pillars Intel should be great at? What are the areas where Intel cannot afford to be behind? There needs to be a baseline. We started mapping it out.”

Koduri said the team looked at its capabilities in each specific area, and it ranked them with colors red (behind rivals), yellow (parity), or green (leadership). Keller said that in six months he has been able to better understand all of the things Intel’s tens of thousands of engineers do. He said he prefers to think of himself as an “execution architect,” or someone who is a “friend of the transistor” and makes things happen on a daily basis, rather than focusing on a long quest. He also wants to make “engineering more fun by lowering the friction” that gets in the way.

“Intel’s mission is not to do 5 percent better every year,” Keller said. “Our mission says we are building stuff that changes the world in unknowable ways. Engineers love that stuff, and they work for love.”

Intel’s answer includes a renewed focus on the entire system. It plans to concentrate its engineering resources on driving innovation in advanced manufacturing processes and packaging, new architectures to speed up specialized tasks like AI and graphics, super-fast memory, interconnects, embedded security features, and common software to unify and simplify programming for developers across Intel’s compute roadmap. Talk on Tuesday centered around those architectural efforts.

“We will see more changes in architecture in the next 10 years than we saw in the last 50,” Koduri declared. “What if petaflops of compute power and petabytes of data are a few single-digit milliseconds away from every person on the planet?”

Foveros 3D packaging

Above: Foveros can sandwich two chips in the 3D space where only one fit before.

Image Credit: Intel

To demonstrate its progress, Intel showed off a new 3D packaging technology called Foveros, which for the first time brings the benefits of 3D stacking to enable logic-on-logic integration. It’s a way to put a couple of chips together vertically in a package and shorten the distance electrical signals have to travel, thereby improving efficiency and power consumption for the whole system.

Intel said Foveros paves the way for devices and systems combining high-performance, high-density, and low-power silicon process technologies. Foveros is expected to extend die stacking beyond traditional passive interposers and stacked memory to high-performance logic — such as CPU, graphics, and AI processors — for the first time.

“We will leverage Foveros across the entire product line,” Koduri said.

Above: A demo of Intel’s Foveros 3D chip stacking technology.

Image Credit: Dean Takahashi

The technology provides tremendous flexibility as designers seek to “mix and match” intellectual property blocks with various memory and I/O elements in new device form factors. It will allow products to be broken up into smaller “chiplets,” where I/O, SRAM (a kind of fast memory), and power delivery circuits can be fabricated in a base die, and high-performance logic chiplets are stacked on top.

Intel expects to launch a range of products using Foveros, beginning in the second half of 2019. The first such product will combine a high-performance 10-nanometer compute-stacked chiplet with a low-power base. It will enable the combination of world-class performance and power efficiency in a small form factor, Intel said.

Foveros is the next leap forward, following Intel’s breakthrough Embedded Multi-die Interconnect Bridge (EMIB) 2D packaging technology that was introduced in 2018.

Sunny Cove CPU architecture

Above: Intel’s Core and Atom CPU roadmaps.

Image Credit: Intel

Intel also showed off Sunny Cove, its next-generation CPU microarchitecture designed to increase performance per clock and power efficiency for general-purpose computing tasks. Sunny Cove includes new features to accelerate special purpose computing tasks, like AI and cryptography. Intel has previously talked about 14-nanometer chips, like Cascade Lake and Cooper Lake.

Sunny Cove will be the basis for Intel’s next-generation server (Intel Xeon) and client (Intel Core) processors later next year. Sunny Cove features include improved designs that allow it to execute more operations at the same time, in parallel. Ronak Singhal, an Intel fellow, said that Sunny Cove finds ways to make processing wider, deeper, and smarter, with more work done in parallel and larger caches to improve latency.

It will also have new algorithms to reduce latency, or interaction delays; increased size of key buffers and caches to optimize data-centric workloads; and architectural extensions for specific use cases and algorithms.

For example, Sunny Cove has performance-boosting instructions for cryptography, such as vector AES and SHA-NI, and other critical use cases, like compression and decompression.

Sunny Cove also enables reduced latency and high throughput, as well as offering much greater parallelism, which is expected to improve experiences from gaming to media to data-centric applications. A follow-up chip, Willow Cove, will also arrive in 2019 with more security features, and another one, Golden Cove, will arrive in 2021.

Meanwhile, Intel continues to work on its low-end processor architecture, Atom, for devices that need good battery life. One chip, Tremont, will debut in 2019. Another, Gracemont, is coming in 2021, and Nextmont should arrive in 2022 or 2023.

Koduri also said that Intel is continuing to pursue high-end AI chip designs and field programmable gate arrays (FPGAs).

Gen11 integrated graphics

Above: Intel Gen11 has advanced features like foveated rendering, where the peripheral parts of an image are fuzzy in the name of better performance.

Image Credit: Dean Takahashi

Intel unveiled new Gen11 integrated graphics with 64 enhanced execution units, more than double previous Intel Gen9 graphics (yes, for some reason Gen10 wasn’t a good comparison to make), that are designed to break the teraflop barrier. The new integrated graphics will be delivered in 10-nanometer processors beginning in 2019.

The new integrated graphics architecture is expected to double the computing performance-per-clock compared to Intel Gen9 graphics. The integrated graphics are considered part of another chip, like the Intel processor, while discrete graphics like the kind Nvidia or AMD make are separate chips. While discrete graphics processing units (GPUs) are sexy, Intel fellow and chief GPU architect David Blythe noted that a billion consumers use Intel integrated graphics today. Making games work better on those machines is a priority for Gen11, Blythe said.

With teraflop performance capability, this architecture is designed to increase game playability. At the event, Intel showed Gen11 graphics nearly doubling the performance of a popular photo recognition application when compared to Intel’s Gen9 graphics. Gen11 graphics is expected to also feature an advanced media encoder and decoder, supporting 4K video streams and 8K content creation in constrained power envelopes.

Gen11 will also feature Intel Adaptive Sync technology, enabling smooth frame rates for gaming. (Both AMD and Nvidia have had this for a while, but Intel is adding it to base systems that sell on the order of 200 million units a year.)

Intel also reaffirmed its plan to introduce a discrete graphics processor, dubbed Xe, by 2020. Koduri said it will be good but that Intel isn’t going to comment further yet. This, of course, is what we all want to hear about, as it will redefine competition with graphics rivals AMD and Nvidia. There will be two variants of Xe: one for the datacenter and one for client platforms, Koduri said.

“One API” software

Bob Noyce's backyard.

Above: Bob Noyce’s backyard. One view.

Image Credit: Dean Takahashi

Intel announced the “One API” project to simplify the programming of diverse computing engines across CPU, GPU, FPGA, AI, and other accelerators. The project includes a comprehensive and unified portfolio of developer tools for mapping software to the hardware that can best accelerate the code. A public project release is expected to be available in 2019.

Koduri said that Intel has more than 15,800 software programmers and that they are working on this technology so that “no transistor is left behind.” That sounds good, though I’m not sure exactly what he meant.

“We have gotten a huge religion around software in the last 12 months,” Koduri said.

Better memory and storage

Above: The house that memory built.

Image Credit: Dean Takahashi

Intel discussed updates to Intel Optane technology (a 3D Xpoint memory) and the products based upon that technology that aims to close the gap between slow, permanent storage devices, like solid-state drives (SSDs) and hard drives, and faster, impermanent memory, such as dynamic random access memory (DRAM).

Intel Optane DC persistent memory is a new product that converges memory-like performance with the data persistence and large capacity of storage, said Frank Hady, chief architect for Optane products. The technology brings more data closer to the CPU for faster processing of bigger datasets, like those used in AI and large databases. Its large capacity and data persistence reduces the need to make time-consuming trips to storage, which can improve workload performance.

The company also showed how SSDs based on Intel’s 1 terabit QLC NAND die move more bulk data from hard disks to SSDs, allowing faster access to that data.

The combination of Intel Optane SSDs with QLC NAND SSDs will enable lower-latency access to data used most frequently. Taken together, these platform and memory advances complete the memory and storage hierarchy, providing the right set of choices for systems and applications.

Feeding the beast

Above: Intel’s architecture plan

Image Credit: Intel

This kind of new memory is what you need in order to keep feeding data to “the beast,” the main processor or FPGAs or GPUs.

Recapping the day, Renduchintala said Intel’s product vision is to deliver a mixture of architectures — including scalar, vector, matrix, and spatial — “exquisite solutions, fed by disruptive memory hierarchies.” Intel will bring in the new technologies, like 3D packaging, when they are ready and will iterate on them until the whole system works better.

Renduchintala said that Intel isn’t just in the CPU business, that it’s more like “XPU,” where the “X” could refer to a CPU, a GPU, an FPGA, or something else.

“I summarize this as the Intel advantage,” he said.

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