This article is part of the Technology Insight series, made possible with funding from Intel.

When it comes to manufacturing technology, we’re taught that smaller transistors are better. They switch faster and use less power. They take up less space, carving out room for more cores, more cache, and ultimately better performance. And when foundries can fit more dies onto the same sized silicon wafer, costs go down. It’s no surprise that the technology world anticipates each process shrink with bated breath.

But not all nodes are created equal. Back in 2017, Mark Bohr, Intel’s former director of process architecture and integration, claimed the company’s 14nm process had about a three-year lead over the competition’s 10nm technology with similar density. In this case, density refers to the number of transistors packed into a unit of area (typically square millimeters). Interestingly enough, he also showed that enhanced versions of Intel’s 14nm node would actually outperform its first 10nm effort, albeit at higher active power consumption.

Today, enhanced 10nm transistors play a key role in helping Intel’s new Tiger Lake mobile platform hit higher clock rates compared to the previous-gen Ice Lake design. The transistors are simultaneously faster and more efficient than any preceding process, rivaling the competition’s 7nm technology. How is such a thing possible? Intel says it’s focusing on manufacturing innovations beyond traditional feature scaling, such as new materials and device architectures. Intel calls the resulting node 10nm SuperFin.

“The combined power of these innovations enable us to deliver a dramatic processor performance boost that makes it the largest single node enhancement in Intel history,” says Dr. Ruth Brain, Intel fellow in the technology and manufacturing group. Let’s take a closer look at the technologies supercharging the 10nm process with what Dr. Brain claims is nearly the equivalent performance of a full node transition.

Key points

  • The 10nm SuperFin node is a long-awaited enhancement to Intel’s first 10nm manufacturing process
  • Intel implemented a number of innovations beyond smaller transistor features to realize major gains
  • A planned 10nm Enhanced SuperFin process will be tailored for data center CPUs and GPUs

Performance and power are more than just the node name

Once upon a time, nodes were referred to by minimum feature size—typically the transistor gate length, or the distance electrons travel from the transistor’s source to drain. This changed gradually as as other parts of the transistor got smaller and gate lengths stopped scaling as aggressively.

As far back as 2017, we knew it’d take a couple of node enhancements for Intel’s 10nm technology to surpass the mature 14nm process.

Above: As far back as 2017, we knew it’d take a couple of node enhancements for Intel’s 10nm technology to surpass the mature 14nm process.

Image Credit: Intel

Today, node names largely represent generational progress. They don’t reflect gate length; the pitch, width, or height of modern field-effect transistor (FET) fins; or even transistor density. It’s consequently difficult to cut through the marketing and compare competing process technologies based on their names.

But because Intel struggled to bring 10nm to production, the company must now endure contrasts between its 10nm transistors and the 7nm nodes from TSMC and Samsung. Fortunately for Intel, the 10nm node holds its own, even though naming suggests otherwise. Heavy investment into beefing up 10nm helped Intel facilitate a ~2.7x density improvement over 14nm, packing more than 100 million transistors into a square millimeter of die area.

“The aggressive scaling was enabled by innovations that moved beyond the transistor device to the metal interconnects and ultimately cell level and beyond,” said Brain at Intel’s recent Architecture Day 2020.

The long road to 10nm

One such innovation is self-aligned quad patterning, a process used to overcome lithography resolution limits and create very dense interconnects. Intel’s 10nm node is the first to use self-aligned quad patterning on the lowest metal layers to drive interconnect pitch scaling from 52nm at 14nm manufacturing down to 36nm, bringing the wires connecting transistors closer together.

Those same metal layers also employ cobalt local interconnects for the first time, reducing the effects of electro-migration and halving via resistance compared to copper at the narrowest interconnect pitches.

Intel’s 10nm process incorporates contact over active gate (COAG) technology, too. According to Kaizad Mistry, co-director of logic technology development at Intel, moving the contact from its traditional position next to the transistor to right above it improves area scaling by 10%.

Contact over gate technology is one of the features of Intel’s 10nm process, which helps improve area scaling by roughly 10%.

Above: Contact over gate technology is one of the features of Intel’s 10nm process, which helps improve area scaling by roughly 10%.

Image Credit: Intel

Further density scaling at 10nm is achieved by halving the number of spacer, or dummy gates, between cells. At 14nm, Intel used one dummy gate at each end of its cell. With two cells side by side, that looked like a pair of adjacent dummy gates. Now cells can share one gate, delivering an additional ~20% area scaling.

Refining the technologies that went into Intel’s 10nm process did delay volume production more than the company would have liked. However, they ultimately laid a foundation for the enhancements found in 10nm SuperFin. “The era of getting massive performance boosts from simply shrinking transistor features is behind us,” Brain said. Now, improvements made to the process stack promise a substantial boost.

10nm SuperFin = SuperMIM + Redefined FinFET

After years of tacking pluses onto its 14nm intranode enhancements, Intel is being a little more creative with its nomenclature. 10nm SuperFin is derived from a new Super MIM (metal-insulator-metal) capacitor design and what the company calls a redefined FinFET.

Some of the 10nm SuperFin’s improvements focus on enhancements to Intel’s transistor design.

Above: Some of the 10nm SuperFin’s improvements focus on enhancements to Intel’s transistor design.

Image Credit: Intel

“Within the transistor, we improved epitaxial growth of crystal structures on the source and drain, increasing the strain and decreasing resistance,” said Brain. As a result, more current can flow through the channel. Enhancements to the FinFET’s source and drain architecture further improve channel mobility, enabling charge carriers like electrons to move more quickly. Moreover, a larger gate pitch creates an opportunity for higher drive current, servicing performance-sensitive chip functions. Together, those transistor-level improvements allow 10nm SuperFin to hit higher clock rates at any set voltage compared to Intel’s original 10nm process.

The 10nm SuperFin process uses thinner barrier materials that reduce vertical interconnect access (via) resistance by 30%. If you’re interested in some heavy reading, check out this presentation by Dr. Paul Besser at the Northern California Chapter of AVS back in 2017. But in brief, he points out that resistance is of increasing concern as interconnect pitch scales down (hence the switch to cobalt for certain metal layers). Using new barrier materials for 10nm SuperFin further address the resistance problem, improving interconnect performance.

The Super MIM cap increases capacitance by up to 5x, Intel claims. The result is a voltage reduction that improves performance.

Above: The Super MIM cap increases capacitance by up to 5x, Intel claims. The result is a voltage reduction that improves performance.

Image Credit: Intel

Even more significant is the Super MIM capacitor, which Intel says increases capacitance by 5x compared to the industry standard. “This innovation is enabled by a new class of Hi-K dielectric materials stacked in ultra-thin layers just several angstroms thick to form a repeating superlattice structure,” said Intel’s Brain during her presentation. The capacitance increase enables a voltage reduction that, again, pays dividends in performance.

Putting rubber to the road with Tiger Lake

With just one intranode enhancement, 10nm SuperFin delivers gains almost equivalent to a full node transition, the company claims. If that proves true, the Tiger Lake system-on-chip (SoC) due out this year and built using 10nm SuperFin should be formidable.

Intel says it optimized Tiger Lake for the 10nm SuperFin process. So, the SoC’s quad-core Willow Cove CPU is free to hit dramatically higher frequencies within the same power envelopes as its predecessor. That fact alone is expected to confer a greater than generational performance improvement.

In practice, 10nm SuperFin allows the upcoming Willow Cove core to operate at higher clock rates for any fixed voltage or reduce voltage at a given frequency.

Above: In practice, 10nm SuperFin allows the upcoming Willow Cove core to operate at higher clock rates for any fixed voltage or reduce voltage at a given frequency.

Image Credit: Intel

SuperFin should help Intel’s Xe graphics architecture sustain higher clock rates, too. Considering Tiger Lake also boasts 50% more Execution Units than the previous-gen Ice Lake SoC, it’s a foregone conclusion that 3D workloads will see a pronounced uplift.

A promising future beyond 10nm

The first products based on Intel’s 10nm process weren’t as strong as those built using mature enhancements of the 14nm node. This changes with 10nm SuperFin. Apparently, the company’s datacenter groups saw what was going on and requested additional features that’d benefit their products as well.

Although Intel’s Architecture Day 2020 was light on information about 10nm Enhanced SuperFin technology, it did say the enhancements would focus on improved interconnect performance for moving lots of data across chips. It’d be safe to say upcoming Xeon and Xe-HP GPUs will capitalize on Enhanced SuperFin to augment Intel’s scalar and vector architectures in a better-together story.


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