Copper wires might be the bottleneck in the way of Moore’s Law

Making transistors — the tiny on-off switches of silicon chips — smaller and smaller has enabled the computer revolution and the $1 trillion-plus electronics industry. But if some smart scientist doesn’t figure out how to make copper wires better, progress could grind to a halt. In fact, the copper interconnection between transistors on a chip is now a bigger challenge than making the transistors smaller.

Transistors will soon be made with circuits that are just 22 nanometers apart. (A nanometer is a billionth of a meter, and a human hair is about 100,000 nanometers thick). But the challenge is now that the resistive-capacitive delay, or RC delay, within the copper interconnect is stopping the transistors from getting faster as they shrink, as is normally the case. The materials are also becoming unreliable at the tiny dimensions.

“Interconnect is the bottleneck going forward,” said Mehul Naik, a distinguished technologist and an interconnect expert at chip equipment maker Applied Materials, in an interview with VentureBeat.

The copper dual damascene technology has been a good solution for about two decades. But Naik said that the 14-nanometer generation of chips might be an “inflection point,” where copper’s resistivity will increase exponentially, blocking attempts to make transistors smaller and faster. The interconnect is now an obstacle to Moore’s Law, the notion dreamed up in 1965 by Intel chairman emeritus Gordon Moore that the number of transistors on a chip will double every two years. Moore’s Law is the engine of progress for electronics, and it’s why your smartphone is as fast as a computer once was and doesn’t burn your hand.

Solving the interconnect problem is critical for the $300 billion chip industry, and it is a topic of discussion this week at a gathering of chip engineers, the International Electron Devices Meeting, in San Francisco. Naik will be part of a panel of experts that includes Robert Aitken, a fellow at ARM Holdings; Jon Candelaria, director of interconnect and packaging sciences at Semiconductor Research Corp.; Dinesh Somasekhar, a senior scientist at Intel Corp.; Zsolt Tokei, program director for nano interconnects at IMEC; and Douglas Yu, senior director of backend research and development at TSMC, Ltd. That list of speakers tells you that a lot of big players in the industry care about this problem.

The engineers are trying to figure out ways to keep the resistance of copper wiring in check. That means they also have to find new materials that serve as insulators for copper. Those insulators have to be better than the low-k dielectric films — which were considered a great breakthrough just a short time ago — that are currently in use. The problem is that the job gets harder over time as chip miniaturization proceeds. At the 5-nanometer to 7-nanometer manufacturing generations — which the industry will reach in 2017 — the copper interconnect problem is probably a showstopper.

“We need to find new materials,” Naik said. “We may have to explore the possibility that we will go away from copper.”

[Image credits: IBM and Applied Materials]