Above: Globalfoundries makes a variety of chip types.

Image Credit: Globalfoundries

VB: Are you tailored to a customer like AMD, or do you feel like your factories are fairly general-purpose?

Jha: I’d say we work very closely with AMD now, to the point that we definitely do things for AMD which make a big difference to their product. Let’s say somebody has done a CPU core at AMD in 14nm, and they want us to improve the performance. What they want is to not have to redesign that core from scratch. That’s very expensive. They’re working on 7nm already and they only have so many resources. They want incremental improvements, where you get more performance, without having to redesign the entire product.

That’s generally the request we get from customers. We’re very keen to do that ourselves because we don’t want to create new standards or libraries. We have probably 100 partners who will generate IP on our platform. We don’t want to move the technology so much that they have to completely redesign. It’s one thing to re-characterize it. It’s another to redesign. We do optimize a lot for our customers, but within certain constraints.

VB: As far as where you see the chip industry now, what are the overall characteristics of the market like?

Jha: There are two things. One is that there is scaling. There’s 14nm, 12nm that we’re announcing, and then 7nm. We’ll have 7nm available early to middle of next year. We’re well on the path of scaling. 7nm is probably one of the most dramatic changes in PPAC that we’re going to see for a while.

The second part, much more interesting, is that more of the systems are becoming heterogeneous. If you look at the Ryzen chip, what’s happening is the cost of 7nm per square millimeter is much higher than the cost would have been at 14nm. These chips have areas where they absolutely need the benefits of 7nm, but also areas with no need for 7nm. For instance, most CPUs have a memory interface, a display interface, serial links like USB. Those things don’t need to be in 7nm, and they’re becoming an increasing part of the circuit.

People are separating those, leaving them in 14nm and then putting a CPU chip in and putting links to it. There are some performance and architectural tradeoffs that have to be done very carefully, but people are making package choices. Moore’s Law is an economic law, not a physical law. It’s becoming less economic to scale everything in the way that used to be the case earlier. Cost is not coming down at the same rate. Power is not coming down at the same rate. Performance is not going up at the same rate. You can get the scale, but the cost of getting scaling is becoming higher. You have to double-pattern, triple- and quad-pattern lines to get the scale.

Moore’s Law is definitely slowing down, but people are innovating within that constraint. Another thing that’s going on, something probably even bigger, is that more things are getting connected. Wireless integration is becoming even more important. Not only that, but more things are battery-powered, so power consumption is getting more important. PCs used to have 30kw/h of battery. Cell phones have 2-3kw/h battery. IOT devices have 300mw/h battery. It’s a reduction of a factor of 10 in the amount of battery you have available.

Above: One of Globalfoundries’ chip manufacturing sites.

Image Credit: Globalfoundries

Two other things go with that. One, PCs used to run for eight or nine hours on a good day. Even today, it’s hard to get nine hours out of a laptop. Cell phones have to last 24 hours. IOT devices have to last months, if not years. Two, volume has gone down. Your volume is probably more than an order of magnitude of change from a PC to a phone. You go from a phone to an IOT device, there’s more than an order of magnitude.

This is driving technology development on a different vector. That’s not scaling. That’s looking at power. By the way, at ASP the processor in a laptop is maybe $100. The one in this phone is $15. It’ll be a dollar or two in an IOT device. We’re focusing more on cost-effective, power-effective, and connected devices. We believe the growth rate there is much higher.

That’s where you’ve seen our 22 FDX and 12 FDX technologies. They’re planar technologies, not FinFET technologies. They’re much less complex, and the cost of doing the development is much lower. If you had to spend $100 million to develop an IOT device, you could never justify it. What we’re doing is at much lower cost. A set cost for an IOT device has to be dramatically lower. FinFET is always going to be more expensive. You’re not going to see a lot of IOT devices on FinFET.

You’ll see the scaling vector, and that scaling vector is becoming a little slower, because cost is going up and people are applying packaging — they’re stacking memory, for instance, heterogeneous integration of technologies. Then you’re seeing this cost-sensitive connected technology development. We have to support both. 22nm is the last technology you should think about as single-pattern planar technology. 12nm, in my view, is the last optical, cost-effective dual-pattern technology. After that, what 7nm that is initially optical will go to UV in the long run. You’re seeing these discontinuous switches in technology, and you have to think about the architectures and how they pair up with those.

VB: How much do chip factories cost these days?

Jha: It depends what technology. 7nm will be $10-12 billion. 5nm will probably be $14-18 billion. Remember, what happens in our business is you have to invest a large amount of money, and you’re turning capex into operating cash flow. The biggest risk in our business now is only a limited number of people can use leading-edge technologies. Qualcomm, Apple, Nvidia, AMD, and the FPGA guys are the only ones who absolutely need it. We’re leaving out Intel. Even there, their success and their impact in the foundry business has yet to be determined, quite frankly.

Above: AMD’s Ryzen chip

Image Credit: AMD

The vast majority of the mobile space is not actually at the leading edge. Only the premium tier is at the leading edge, and that’s now less than 15-20 percent. There’s another economic argument. At the leading edge, it costs you somewhere between $250 and $500 million to develop a chip. Assuming your R&D to revenue ratio is five — you’re spending 20 percent, very much on the high end of all tech companies. It’s usually between 10 and 20 percent, so you’re getting five to 10 times the revenue. You need to make $2.5-5 billion in revenue to develop that.

The number of markets that justify that are shrinking. Servers can justify it. Graphics can justify it. Mobile can justify it. But increasingly, you can only justify it at the premium tier. At the lower tier you can’t. All of that plays into that shrinking. There are really only four companies in the world that can develop leading-edge technologies, and Intel’s technology isn’t generally available. That leaves TSMC, ourselves, and Samsung. TSMC and ourselves are the only ones with a broad range of technologies. If you wanted to combine RF technology with leading-edge technology, TSMC and ourselves are the only ones who could produce it. Samsung tends only to be a leading-edge company.

VB: Given that outlook, are you worried that advances in computing could slow down?

Jha: I’m not. Advances in computing will happen in three different ways. IPC, instructions per cycle, if you look at that it’s slowed down considerably already. Over the last three or four years, architectural improvements haven’t driven a dramatic number of IPC. What’s interesting is that AMD’s success right now is purely architectural. Intel has not really been making architectural advances. It’s mostly been semiconductor technology. I think you’ll see that architectural improvement will drive more than semiconductor technology.

What you can do is pack in more circuit. That goes some way toward the lack of improvement. But architecture is the more efficient way to improve your technology. AMD’s success is architectural success. There’s no doubt that AMD, at 14nm, is competing against Intel’s 10nm because of its architecture, not because of the semiconductor technology alone.

Second, we’ll see packaging solutions. We’ll see stacked memory to provide memory bus bandwidth that wasn’t possible before. You’ll see more 3D and 2.5D packaging. The third thing is solving system problems, as opposed to just CPU problems: combining cameras, understanding AI, using non-von Neumann architectures to accelerate the next-generation problems. Next-generation problems, the vast majority of that will not be about browsing or gaming, but about understanding images and making real-time decisions on structured data.

Von Neumann architectures are not ideal architectures. Non-von Neumann doesn’t necessarily need the scale. We have, what, about 80 to 100 billion neurons in our brains? Sixty percent of our neurons are for pattern recognition. As far as I can tell, we’ve just started our journey into pattern recognition. The feature size of our brains is measured in microns. We’re nanometers and nowhere near. It’s not about scaling. The energy efficiency of our brain, by the way, is about a thousand times higher relative to the same kind of computing, with micron features. It’s about architecture. It’s not just about scale.

Now, I’m not saying we shouldn’t continue to scale. If you want to pack server cores into a big 700mm square chip, scaling matters. But the number of applications where it continues to matter will become lower.