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SiFive is designing open and customizable processors based on the RISC-V architecture. And today the Silicon Valley startup announced a series of processor cores that it says are more power-efficient than ARM’s competing processor designs.

San Mateo, California-based SiFive has announced availability of its E2 Core IP Series chips, which are configurable microcontroller cores that use less power and can cost less than other processors. Like ARM, SiFive licenses its chip designs to other companies, which customize them and manufacture them on their own. But compared to ARM, it takes a more open approach to the ownership of the designs.

The E2 Series extends SiFive’s product line with two new standard cores, the E21, which provides mainstream performance for microcontrollers, sensor fusion, minion cores, and smart internet of things (IoT) markets. It is also launching the E20, a power-efficient SiFive standard core designed for microcontrollers, IoT, analog mixed signal, and finite state machine applications.

Additionally, the company announced enhancements to its existing standard E3 and E5 Core IP Series.

The SiFive E20 and E21 are designed for markets that require extremely low-cost, low-power computing but can benefit from being fully integrated within the RISC-V software ecosystem.

Fully compatible with the same software stack, tools, compilers, and ecosystem vendors as other higher performance SiFive cores, the E2 Series enables these new markets to take advantage of the robust software ecosystem that has been exponentially growing since SiFive first introduced commercial RISC-V cores in 2016.

Both cores are fully synthesizable and verified soft IP implementations that scale across multiple design nodes. Customers can either directly leverage the silicon-proven standard SiFive Core IP, like the E21, or customize it.

“SiFive’s Core IP is the foundation of the most widely deployed RISC-V cores in the world, and represent the lowest risk and fastest path to customized RISC-V based SoCs,” said Yunsup Lee, chief technology officer at SiFive, in a statement. “Our Core IP Series takes advantage of the inherent scalability of RISC-V to provide a full set of customizable cores for any application — from tiny microcontrollers based on our new E2 Core IP Series to our previously announced, Linux-capable, multicore U Core IP Series.”

SiFive will demonstrate the E21 at the Design Automation Conference at San Francisco’s Moscone Convention Center, through June 27, in the RISC-V Foundation booth.

The company has raised $64 million to date from Sutter Hill Ventures, Spark Capital, Osage University Partners, and Chengwei Capital, along with strategic partners Huami, SK Telecom, Western Digital, and Intel Capital.

Coremark measures the raw performance of a CPU pipeline, and the SiFive E2 cores’ very efficient design translates to leading performance.

As for ARM comparisons, in particular, SiFive said in an email, “While it’s great to have a better-performing processor, the bigger deal is that RISC-V represents a completely new paradigm for companies adopting it. SiFive RISC-V cores allow customers full access to the RISC-V software ecosystem, which is being built at an exponential, open source speed. The ability for companies to share in the common, robust software ecosystem while still having access to fully customize cores that fit their needs is unique to RISC-V. With the E2 Series, SiFive now provides its customers a full portfolio of RISC-V IP cores from small embedded to high-performance multicore processors, which means RISC-V can now be adopted across the entire product stack.”

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