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Data infrastructure technology solutions from the Santa Clara, California-based company Marvell have already become an industry benchmark. Now the company has expanded its 5nm data infrastructure portfolio with a line of high-performance Prestera carrier switches and its OCTEON 10 data processing units (DPUs).

Marvell’s Prestera switches combine high-bandwidth, high-availability, and resilient switching systems with speed and high-precision synchronization benefits. In particular, the Prestera family’s optimization capability helps network operators scale with their 5G infrastructure needs. The new DX 7321 Ethernet switch is another significant addition to the Prestera line.

Bringing new 5G devices to the carrier market

The DX 7321 aims for the 5G front haul and edge connectivity market. When combined with Marvell’s 5nm OCTEON 10 DPUs, the company claims the switch consumes 50% less power than its peers. The combination strengthens and facilitates the next-gen 5G Carrier Edge network solutions, Marvell says, along with radio access network (RAN) deployment models.

The DX 7321 switch is the fourth in Marvell’s list of carrier switching products. The carrier switch product line can now handle port speed scaling capabilities from 1 to 400Gbps, and aggregate bandwidth may move anywhere between 200Gbps and 1.6Tbps. The introduction of DX 7321 also makes it possible to cater to three types of 5G architectural solutions: Open RAN, vRAN, and traditional RAN.

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Along with the new switch, enhancement also leans heavily on the OCTEON solutions. After introducing OCTEON fusion baseband processors and multicore DPUs, the OCTEON 10 family of products angles itself at demanding workloads. With its capacity to bring in the optimal compute mix and exploit hardware acceleration, data path bandwidth, and groundbreaking I/O, Marvell says, OCTEON optimizes those workloads.

Raghib Hussain, the president of products and technologies at Marvell, believes that the company’s 5nm production expansion and the DPU “set a new bar for power, performance, and footprint, providing the breakthrough technology needed to fulfill the potential of 5G.”

The company has high hopes for the potential collaboration among all its stakeholders. Nokia says it is delighted “to cooperate with Marvell to bring industry-leading silicon technology to market,” and IP Infusion finds it fulfilling “to work with Marvell to bring access and edge networking solutions to customers building high-performance carrier infrastructures.”

Shin Umeda, the vice president of the market research firm Dell’Oro Group, believes that Marvell’s expansion of its 5nm portfolio and introduction of the OCTEON 10 DPU will benefit next-gen infrastructure building, helping to “deliver on 5G’s potential.”

Benefiting from fresh data infrastructure solutions

TSMC’s 3nm process technology-based advanced silicon platform, another introduction to Marvell’s data infrastructure portfolio, would further augment Marvell’s lead. The company’s clients will be able to leverage system-optimized solutions from TSMC, the most advanced semiconductor technology provider in the industry.

The beneficiaries would include a range of industry verticals, such as cloud datacenters, 5G carriers, and the automotive and enterprise markets. The benefits would spread in all three areas of cost, performance, and power requirements. However, the most enticing aspect, Marvell asserts, is that it offers a standards-based silicon platform for multi-chip solutions, combined with a cutting-edge die-to-die interface IP and 2.5D chip-on-wafer-on-substrate (CoWoS).

As far as the die-to-die interfaces are concerned, the benefits are two-pronged. The first interface is a short-reach one that targets the cloud datacenters. The other is an ultra-low-power and low-latency parallel die-to-die interface that offers the industry’s highest bandwidth density. To remain aligned with the 5nm enhancements, both the interfaces are available in 5nm to enable multi-node solutions.

Sandeep Bharathi, executive vice president of Marvell, believes that the 3nm capacity expansion will put “Marvell on the leading edge of technology readiness with early Si validation of critical IPs to enable fast time-to-market.”

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