It isn’t easy to establish a custom chip architecture these days. But Tilera has managed to do that in the past year and now it is moving on to its second generation of products.
Today, San Jose, Calif.-based Tilera is launching two models of its new TilePro family of chips for telecom and networking infrastructure where energy-efficient performance is paramount. The chips are based on the custom Tile architecture that Tilera debuted a year ago.
If Tilera succeeds, it will be able to establish an alternative processor platform for communications customers. It will also prove that the day of launching new chip architectures isn’t dead, suggesting that there is still room for innovative chip design in a decades-old industry as new computing problems and applications surface.
Each chip has either 36 or 64 tiles (processing cores). They’re connected via a unique communications structure known as a mesh. Anant Agarwal, an MIT professor who is chief technology officer, said that the mesh allows the tiles to maximize processing performance without running into the typical communications bottlenecks that other chips face.
As an example, a tile can process a piece of data and deliver the result to the next tile, which can start using that data right away. Other processors can do that, but not during the same tick of the clock. This makes the chips faster and it allows them to scale. That is, you can add lots of tiles to a chip and its performance will keep on improving. With other chips, the bottlenecks are so severe that 48 cores might not be any more powerful than 32.
“Over time, there have been fewer and fewer chip architectures in the market,” Agarwal said. “To launch a new one, you have to do something disruptive.”
He said that Tilera, with 64 tiles on a chip, can put more processing cores on a chip than rivals such as Cavium Networks and RMI — both of whom use the Mips architecture. Tilera also competes with Cswitch, Ambric, Stream Processors, PicoChip and Netronome. Bigger companies such as Freescale, Intel and others also have alternatives to offer (Intel’s general-purpose chips, for instance) in this market. The Tilera chips compete with digital signal processors, field-programmable gate arrays, custom chips and general-purpose processors. That gives the company a fairly wide array of high-end embedded chip markets to target.
A couple of chip experts I asked about the overall architecture (not the new chips) are skeptical.
“There is merit to the mesh idea,” said Linley Gwennap, an analyst at the Linley Group in Mountain View, Calif. “But there is a question as to whether there are that many applications that need all of that performance.”
Peter Glaskowsky, former editor of the Microprocessor Report and a blogger for CNET, said that he has written about a couple of dozen chip designs like Tilera’s from companies such as BOPS, ClearSpeed, MathStar, Micron, NEC, PACT and others. None of them have seen much commercial success because there are big technical hurdles to building chips with an array of processors. The challenges include getting the interconnections right, the difficulty of parallel programming, the dearth of applications that need this performance, and competition from simpler CPUs and FPGAs, Glaskowsky said. As far as Glaskowsky is concerned, Tilera’s architecture has the same trade-offs that others do.
Tilera is targeting the chips at high-end networking equipment that would otherwise use digital signal processing chips from Texas Instruments. Tilera says that its high-end TilePro64 chip has 15 times better performance than TI’s DaVinci DM6467 series DSP. It also has 35 times the performance per watt of the Intel Xeon quad core chips running at 3 gigahertz.
Agarwal (pictured left) says the solution is easy to program because you can write code for the chips in the popular C languages. That gets programmers over the hump that has stymied new architectures in the past: Why would I want to program for something totally new and untested? With Tilera’s programming model, it’s a trivial matter to get Linux code running on the chips.
The new chips are up to 2.5 times faster than the first Tile chips that came out a year ago but they consume only about 5 percent more power. So far, the company has won over 45 customers. Some targets include servers for video web sites that need to transcode, or convert video from one format to another, such as Google’s YouTube. Top Layer Networks plans to use Tilera in a new intrusion-detection appliance aimed at sifting through incoming web traffic at a company for anything suspicious. Napatech is shipping a network card that offloads network traffic processing from a server. BDTI, a chip consulting company, estimated that the Tile chips are faster than any other chips targeted at wireless infrastructure.
Agarwal founded the company in 2004 based on his new idea for interconnecting different cores on a single chip. The first chip debuted in 2007 and the new ones have smarter memory. Tilera has raised $39 million in two rounds of funding. Investors include Bessemer Venture Partners, Columbia Capital, Venture Tech Alliance (TSMC’s venture arm), and Walden Capital Partners. The company now has 75 employees.
The chip prices range from $500 to $900. Volume shipping is starting and Agarwal expects sales revenues to kick in during the second half of the year. Meanwhile, he said that Tilera is raising money right now.
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