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Battery-saving chip startup SuVolta raises $17.6M

SuVolta, a chip startup that says it can cut power consumption by 50 to 90 percent when coupled with other techniques for lowering voltage, said today it has raises $17.6 million in a new round of funding.

The company’s technology is a fundamental breakthrough, and a rare one, since most venture investments go into applications these days, not core technology.

The funding came from new investor Bright Capital as well as existing investors Kleiner Perkins Caufield & Byers, New Enterprise Associates, August Capital, NEA, Northgate Capital, DAG Ventures and others.

The Los Gatos, Calif.-based company, which came out of stealth mode in June, recently disclosed the first details of how its low-power transistor technology, dubbed Deeply Depleted Channel (DDC), works. The technology will allow for better low-power chips for at least the next couple of generations through sub-20-nanometer production. (A nanometer is a billionth of a meter.)

“SuVolta’s revolutionary PowerShrink transistor is a stunning and disruptive innovation, a true game-changer,” said John Doerr, partner at Kleiner Perkins, in a statement. “It solves the semiconductor industry’s greatest challenge – power – without requiring billions of dollars investment in new fab facilities and chip designs. So partners and investors are racing to exploit this enormous opportunity.”

Chip fundings are rare these days. The Global Semiconductor Alliance said that funding for chip industry suppliers was $272.2 million in 2010, down from $717.5 million in 2007, with 2011 tracking at half the rate of last year.

The DDC transistor reduces threshold voltage variability and enables continued shrinkage of chip circuits. The structure on a transistor works by forming a deeply depleted channel when a voltage is applied to the transistor. Fujitsu has been able to use the technology in a test memory chip known as an static random access memory (SRAM), which can operate below 500 millivolts with the SuVolta technology. In that test chip, voltage was reduced two-fold and the signal-noise ratio was improved two-fold.

If it works across all sorts of chips, it could extend battery life on one end of the computing spectrum and reduce the spiraling electrical costs for servers and supercomputers.

The DDC has different regions that allow for different levels of flow of electrical current. The design lowers the operating voltage by 30 percent and results in less “leakage,” or the unintended loss of electrical energy. Overall, the result is that the transistor allows for multiple voltage settings, which is essential for today’s low-power products, said Scott Thompson, chief technology officer, in an interview.

Techniques like this are needed because the manufacturing gains of shrinking chips — where, per Moore’s Law, the observation that the number of transistors on a chip doubles with each generation every couple of years — isn’t reducing costs or providing performance gains like it once did. Thompson said he believes that the transition between chip manufacturing generations will slow down, so chip makers will need a solution like SuVolta’s to make continued advances.

Bruce McWilliams, president and chief executive at SuVolta, said the technology, which is available for license, has drawn a huge amount of interest from chip makers and designers.

“Power is now the biggest design constraint for electronic products,” he said. “This funding demonstrates the excitement surrounding our technology which dramatically reduces power consumption in ICs.”

SuVolta believes it can offer foundries — such as Taiwan Semiconductor Manufacturing Co. — an alternative to a rival revolutionary Intel technology known as Tri-Gate. The alternative is an important one because other chip makers want to keep up with Intel. To do so, they would ordinarily have to invest billions of dollars in chip manufacturing technology and build a new factory. But SuVolta’s technology can be used in existing factories with existing equipment and existing chip designs, SuVolta chief technology officer Scott Thompson told us earlier. Were it not for this kind of technology, Thompson said, “the foundries would be five years behind Intel.”

Intel announced Tri-Gate earlier this year and said it will use 3D structures to pack more (FinFET) transistors into a given space, cutting power consumption by 50 percent and improving performance by 37 percent. SuVolta attacks a problem called transistor variation. It minimizes the electrical variation in each of the millions of transistors on a chip, allowing for efficiency improvements. On the manufacturing level, SuVolta merely tweaks the “recipe” for making a chip.

PowerShrink will be in production with Fujitsu in 2012, but others are looking at the technology as well.

SuVolta was founded in 2006 under the name DSM Solutions and has 45 employees. To date, the company has raised $58.6 million. SuVolta originally pursued a technology called JFETs to reduce power in digital products. But the company concluded that wouldn’t work because it required customers to invest in new infrastructure. The company brought in McWilliams and then Thompson, who then crafted a product strategy that was more realistic. That led to the May 2010 funding of $22 million from KPCB, August Capital and NEA.

Broadcom, Cypress Semiconductor and ARM have publicly endorsed SuVolta’s technology.

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