Xilinx hopes that its adaptive compute acceleration platform (ACAP) will help datacenters deal with a tsunami of computing demands from artificial intelligence. And the chip maker is announcing today it is shipping Versal ACAP, its first chips that use the technology.
Xilinx spent more than $1 billion and four years of development time to make the new kind of programmable chip.
The idea is to create easy-to-program chips that can be adapted to run just about any kind of AI software. The chips are built with 7-nanometer manufacturing technology, and San Jose, California-based Xilinx is shipping its first Versal AI Core series and Versal Prime series chips to multiple customers through the company’s early access program.
Versal is the industry’s first chip that uses ACAP, a new category of heterogeneous compute devices with capabilities that far exceed those of conventional central processing units (CPUs), graphics processing units (GPUs), and field programmable gate arrays (FPGAs).
An ACAP is a highly integrated, multicore, heterogeneous compute platform that can be changed at both the hardware and software levels to dynamically adapt to the needs of a wide range of applications and workloads in datacenter, automotive, 5G wireless, wired, and defense markets.
Built to be natively software programmable, the Versal ACAP architecture features a flexible, multi-terabit-per-second network-on-chip (NoC). The NoC integrates all engines and key interfaces, making the platform available at boot and easily programmed by software developers, data scientists, and hardware developers alike.
“Having our first Versal ACAP silicon back from TSMC ahead of schedule and shipping to early access customers is a historic milestone and engineering accomplishment. It is the culmination of many years of software and hardware investments and everything we’ve learned about architectures over the past 35 years,” said Victor Peng, CEO of Xilinx, in a statement. “The Versal ACAP is a major technology disruption and will help spark a new era of heterogeneous compute acceleration for any application and any developer.”
Developed in TSMC’s 7-nanometer process technology, the Versal ACAP portfolio combines software programmability with dynamically configurable domain-specific hardware acceleration and the adaptability to enable businesses to react to innovation. A mix of next-generation scalar engines for embedded compute, adaptable engines for FPGA silicon programmability, and intelligent engines for AI inference and advanced signal processing deliver dramatic improvements in raw performance and performance per watt compared to CPU and GPU implementations, according to the company.
The Versal AI Core series delivers the portfolio’s highest compute and lowest latency, enabling breakthrough AI inference throughput and performance through the AI Engine. The series is optimized for cloud, networking, and autonomous technology, offering what Xilinx calls the highest range of AI and workload acceleration available in the industry. The Versal Prime series is designed for broad applicability across multiple markets and is optimized for connectivity and in-line acceleration of a diverse set of workloads.
Both the Versal AI Core series and Versal Prime series include multiple devices, each with dual-core Arm Cortex-A72 application processors, dual-core Arm Cortex-R5F real-time processors, over 2 million logic cells of adaptable hardware, and over 3,000 DSP engines optimized for high-precision floating point and low latency. Versal AI Core devices offer up to 400 AI Engines optimized for AI inference and advanced signal processing workloads.
The Versal portfolio includes four additional series of devices, each architected to deliver scalability and AI inference capabilities for applications across diverse markets, from cloud and networking to wireless communications, edge computing, and endpoints.
The Versal AI Core and Versal Prime series will be generally available in the second half of 2019. Xilinx will show working chips in products at the Xilinx Developer Forum on October 1-2 in San Jose, California.
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