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It was only a matter of time before machine learning transformed the world of chip design. Cadence Design Systems, which makes design tools that engineers use to create chips, is using it to make chip engineers far more productive with its Cerebrus Intelligent Chip Explorer machine learning tool.

Automating chip design (electronic design automation, or EDA) has been evolving for decades, with a hierarchy of tools operating at different levels of abstraction. Cadence got started in 1988 with the goal of using the benefits of computing to design the next generation of computing chips. But engineers have found it increasingly difficult to keep up with the intricate designs for chips that have billions of on-off switches, dubbed transistors. The process of design has become like trying to keep track of all of the ants on the planet.

With machine learning, Cadence Design Systems has been able to add an extra layer of automation on top of the design automation tools engineers have been using for many years, Kam Kittrell, senior product management group director in the Digital & Signoff Group at Cadence, said in an interview with VentureBeat.

The results are pretty awesome. With machine learning, the company can get 10 times better productivity per engineer using the design tools. And they can get 20% better power, performance, and chip area improvements. That’s a huge gain that could ultimately make each chip more affordable, reliable, and faster than it otherwise would have been, Kittrell said. That could mean billions of dollars saved.

This kind of productivity gain is necessary as Moore’s Law, the metronome of the chip industry, has begun to slow. The law predicts that chip performance will double every couple of years, but lately the gains from moving to a new generation of manufacturing have been limited, as we’re entering miniaturization technology on the atomic level and running into barriers from the laws of physics.

Meanwhile, with billions of transistors per chip, engineers who worked on chips a few generations ago, like 28-nanometer chips, can barely function with the requirements for chip design of today’s 7-nanometer chips, where the width between circuits is seven billionths of a meter.

“These are three-dimensional puzzles,” Kittrell said.

Enter machine learning

Cadence's headquarters in San Jose, California.

Above: Cadence’s headquarters in San Jose, California.

Image Credit: Cadence Design Systems

With compounding pressure to deliver new chips more quickly than ever before, engineers have to become increasingly efficient. Machine learning offers an answer, Kittrell said.

Just as today’s “intelligent” consumer devices provide users with information at their fingertips, machine learning automates chip design processes so engineers can complete projects “intelligently,” faster and with fewer mistakes. Machine learning also creates a level engineering playing field, whether you’re an established semiconductor player, a company outside the industry that has brought chip design in-house, or a small startup.

“There have been some refinements over time for chip design, but it’s been basically the same way. And so it’s been getting more and more complicated for an engineer to take a chip through to completion,” Kittrell said. “For example, someone who may be very good at building chips at 28 nanometers will have a huge learning curve to do a five-nanometer chip today. The technology has changed so much.”

Cerebrus doesn’t replace the flow of tools and the way humans interact with the tools. But it works as a driver’s assistant, Kittrell said.

“Power, performance, and area are always the key objectives that anyone drives whenever they’re making a chip,” Kittrell said. “It has to be manufacturable. But after that, there’s a squeeze on power and performance and area. And so we use reinforcement learning in our Cerebrus tool. It controls the tool and does experimentation for the engineer in order to find the best solution.”

A helper

Above: Cadence Design Systems was founded in 1988.

Machine learning isn’t threatening the jobs of chip engineers, who are more sought-after than ever, Kittrell said. Rather than replacing them, machine learning has become an engineer’s “helper,” reducing the learning ramp-up time and handling many traditional engineering tasks automatically.

“This is an example where it improves the productivity of the engineer while also delivering better power performance,” Kittrell said.

Cerebrus uses unique machine learning technology to drive the Cadence RTL-to-signoff implementation flow. Here the engineer designs on a level of abstraction where he or she can understand the logical flow of electrons through a chip. Cadence’s existing, earlier tools would take the logical flow and convert it to the physical layout of the chip. The logical level is the Register Transfer Level, and it is converted to the final sign-off tools and actual placement and routing of wiring throughout a chip. There are often multiple ways to implement a logical design in a physical layout, and optimizing that can save a lot of material, energy, and costs.

An engineer can handle this part of the design on one pass. But Cerebrus can take another run through it and improve the results. The engineer delivers the final design in a database format dubbed GDSII, and then it’s off to manufacturing.

“There’s always a push to find a way to optimize for power, performance, and area. This can take a lot of time in the design process. And this is where Cerebrus can help. It can take a list of anything within the RTL to GDSII and do experiments.”

“You don’t have to spend a lot of time training a model upfront in order to get started. Right from the beginning, Cerebrus can start doing searches based on your vector and your design, and within a few runs [it] can find a better solution,” Kittrell said.

From chip design to your living room

Nvidia's Grace CPU for datacenters.

Above: Nvidia’s Grace CPU for datacenters is named after Grace Hopper.

Image Credit: Nvidia

Once the chip designer is done, they hand the design over to the factory engineers. Inside a chip factory, there are hundreds of steps that are like an assembly line to build a chip one layer of material at a time. Robotics handle a lot of the tasks, but machine learning has also been applied to the giant hardware machines that pattern materials on top of chips. This is what it takes to get the latest Nintendo Switch or PlayStation 5 into the hands of the gamer in your family.

The results are as previously mentioned, and they can help many different chip applications in consumer, hyperscale computing, 5G communications, automotive, and mobile design, Cadence said. It scales engineering resources to handle more projects or bigger ones.

Cadence has already deployed the tool to over a dozen customer locations across all of those applications, Kittrell said. Now the company is making the tool available to all customers.

Cerebrus is part of the broader Cadence digital full flow of tools. The machine learning can reinforce engineers, considering solutions that humans might not explore. It also allows design learnings to be automatically applied to future designs, and it offloads work from humans. It enables distributed computing, with better on-premises or cloud-based designs.

Renesas customer Satoshi Shibatani said in a statement that automated design flow optimization is critical for making products quickly, and he said Cerebrus has improved design performance by more than 10%. So his company is adopting the technology for its latest projects. Samsung VP of design technology Sangyun Kim said Samsung Foundry used the Cerebrus tool and saw an 8% power reduction in its chip and 50% better timing, which improved overall performance.

It’s taken a while for machine learning to impact chip design, but it’s hard to find an industry that it won’t impact.

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