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Researchers from CEA-Leti have presented a new three-step approach to test silicon quantum dot arrays. It represents a new step toward the commercialization of quantum computing based on fabrication methods used in classical computing.
The research pertains to testing arrays of linear floating-gate quantum dots (QD) that have been fabricated on fully depleted silicon-on-insulator (FDSOI), which is a substrate sometimes used in regular chip manufacturing as well.
The first characterization step is carried out at room temperature and uses “transistor-like” protocols to gather data at the wafer level within hours. This is followed by a longer QD characterization step at less than 2 K. The third step is a qubit manipulation test at the die-level, which can take days at 100 mK.
Reclassifying outer gates as access gates
One of the findings from the testing procedure was that within the arrays of QDs, the inner gates delivered “state-of-the-art” specifications regarding the threshold voltage (which is when the transistor turns on) and subthreshold slope (how fast the current increases before the threshold voltage is reached).
However, outer gates had more variability due to factors such as dopant fluctuations. Dopants are impurities that are implanted in silicon in order to increase the electrical conductivity of the silicon. As a solution, the researchers proposed using the outer gates as access gates rather than for confinement of the QDs.
A second finding was that a so-called split-gate design requires strict overlay control in order to achieve enough symmetry.
Detecting ‘spurious dots’ at room temp
As a third recommendation, the researchers developed a room-temperature voltage-sweep technique that can check for inner-gate defects. This defect is the cause of “spurious dots” within the qubit layer, and is a major source of yield loss in QD arrays. This means that it causes many defects. Normally, spurious dots are detected using cryogenic testing, but the room-temperature test allows them to be detected earlier.
Lastly, by using the FDSOI material, back gates can be manufactured that draw charges away from the interfaces, which is called back-biasing. However, the classical method to construct these gates uses dopant implantation, which can cause defects. An alternative method was proposed that uses a TSV-like (through-silicon via) metallic back gate electrode.
The research was presented at the VLSI conference in June. “These research results represent a significant step towards addressing the broader silicon spin qubit integration challenges we discussed at last December’s IEDM conference,” said Heimanu Niebojewski, CEA-Leti lead device engineer. “It’s a very encouraging sign of the technology’s maturation.”