The cost can hit $65 million before all is said and done. eASIC, a start-up in Santa Clara, Calif., is working hard on attacking these problems so that chip start-ups -- which are kind of a dying breed in the inappropriately named Silicon Valley these days -- can flourish again. The company has figured out how to reset the cost equation so that even complex chips can be affordable to design and don't take as long to make, said Ronnie Vasishta, chief executive of eASIC.
Since the ante for chips is so big, the number of custom chips that are being designed has declined for the past decade. But since eASIC debuted its start-up friendly design process in 2006, the company has won more than 120 customer designs. Today, it is launching a second generation of its design process, Nextreme 2, that may make its customers even more competitive with the biggest chip makers.
eASIC combines two traditional chips: the application specific integrated circuit (ASIC, a $20 billion market) and the field-programmable gate array (FPGA, a $3.7 billion market). As such, its competitors are big companies that range from Toshiba to Xilinx. Some companies such as Altera , On Semiconductor's AMI Semiconductor division, and a partnership of IBM and Xilinx have tried to create hybrid models of ASICs and FPGAs. And companies such as Tensilica and eSilicon are also trying to cut the high cost and time it takes to design ASICs. But there are built-in trade-offs to the designs. Vasishta says that eASIC's recipe maximizes customization without requiring extensive chip rewiring.
ASIC chips are fast and low cost, but they are expensive to design and take years to finish. FPGAs are generic chips that can be programmed quickly at the last minute to fit a rapid product cycle. But they cost a lot and are slow.
eASIC can fuse these chips by creating generic chips that are inexpensive to make. But it allows for full customization by allowing the customers to add the final layer of metal on top of a nearly-finished generic chip. This kind of customization cuts factory turnaround times and costs because it doesn't take much time (just six weeks) or special design work to add that last metal layer. The upfront design costs can be as low as $20,000 to $100,000, much lower than the cost of designing an ASIC.
The chips therefore have the hybrid benefits of the full customization of ASICs and the short turnaround times and flexibility of FPGAs. The promise of eASIC is that it can make it a lot easier for start-ups to get to market faster. That is why it has been able to raise $80 million to date from Khosla Ventures; Kleiner Perkins Caulfield & Byers; Crescendo Ventures, Evergreen Venture Partners and Advanced Equities. Most recently, the company raised a $48 million round in March.
Getting to 45nm is a big accomplishment, since only 14 other chip makers have made such announcements. Vasishta said that the company started with 90nm technology and decided to skip the 65nm generation. For the past two years, it worked on delivering a 45nm technology that would leapfrog many competitors and put the company in lock step with giants such as Intel in the technology race.
Customers are making chips for a wide range of applications, including security cameras, cameras, smart phones, and a variety of consumer electronics and computing gear. While ASICs often require huge orders to offset the engineering costs, eASIC doesn't require minimum orders. Roughly 30 percent of the company's customers are billion-dollar chip makers, while 40 percent are start-ups.
Customers are expected to use eASIC's tools so that they can begin fabricating the first 45nm designs later on this year. The first product will be a new graphics chip, Vasishta said. Full told, eASIC customers should be able to get into the make with $150,000.