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Chip startup Atomera said it can breathe new life into Moore’s law with better power efficiency for analog chips.

Los Gatos, California-based Atomera said its Mears Silicon Technology Smart Profile — a quantum-engineered film based on 15 years of research and development — is available for licensing to use in 5-volt power and analog electronics.  It could enable certain kinds of electronics to be produced with 20% more working parts per batch of chips produced, and that could yield significant improvements in costs.

The MST Smart Profile is an integration of the films that go with a specific asymmetric transistor design with the details (dopant implants) optimized to create a five-volt power device.

Through a combination of atomic level engineering and advanced material science, publicly traded Atomera is squeezing more capability and capacity out of today’s semiconductor processes. The resulting improvements in power, performance, and area (PPA) — the standard measure of Moore’s law — are effectively enabling the industry to get smaller die size using the same process node.

Moore’s law, first talked about by Intel chairman emeritus Gordon Moore in 1965, became the metronome of the chip industry. It predicted that the number of components on a chip would double every couple of years. And until recently, it held up remarkably well. But as the physical dimensions of chip miniaturization get smaller and approach the level of individual atoms, it’s hard to make advances. And so many have begun to predict a slowing down of Moore’s law and an accompanying slowdown of technological innovation. That’s not good for the economies of the world.

Jeff Lewis, vice president of business development and marketing at Atomera, said in an interview with VentureBeat that half of the world’s semiconductor manufacturers are engaged in conversations with Atomera. And Atomera has collected more than 300 patents related to the tech over the years.

Lewis said that the technology works for 5-volt transistor products.

Atomera is making chips more power efficient.

Above: Atomera is making chips more power efficient.

Image Credit: Atomera

“It gives a substantial improvement in performance and area to help you get about 20% or more chips out on a wafer than you could in the past,” Lewis said. “Transistors are omnipresent. They’re in almost everything we have out there. And in fact, we just saw an article that DDR5 chips can’t ship anymore because of shortage of the power-management devices that go with it.”

Lewis said the creation of the new technology could help address the backlog and supply shortage problems in the industry. He said chipmakers that adopt the tech could get more value out of existing chip factories.

“It’s really a very broadly applicable technology. And what it really does is enhance transistors,” Lewis said. “You’ll get more drive current out of a transistor, and you can use that in a variety of ways.”

While digital chip technologies have benefitted greatly from Moore’s law, there is a significant market for bipolar CMOS-DMOS (BCD) semiconductors that are built today in legacy nodes ranging from 40 nanometers (nm) to 180nm.

BCD is a family of silicon processes, each of which combines the strengths of three different process technologies onto a single chip: Bipolar for precise analog functions, CMOS (Complementary Metal Oxide Semiconductor) for digital design and DMOS (Double Diffused Metal Oxide Semiconductor) for power and high-voltage elements. ST Microelectronics says this combination of technologies brings many advantages: improved reliability, reduced electromagnetic interference and smaller chip area. BCD has been widely adopted and continuously improved to address a broad range of products and applications in the fields of power management, analog data acquisition and power actuators.

According to The McClean Report from IC Insights, the major user of BCD processes is the power management integrated circuits (PMICs) sector, which had a market size of $14.6 billion in 2020 and is forecast to grow to $24.9 billion in 2025. All these chips are like the condiments that go with your hamburger patty, and they’re quite essential to the functioning of any electronic device, said Lewis said.

PMICs are used in nearly all electronic devices. PMICs are required for any device that is powered by a battery or USB connector, and they are used to scale line voltage (110V or 220V) down to semiconductor voltages of 0.9V – 5V. PMICs are now appearing in unexpected applications – they are now included on DDR5 modules rather than on the motherboard – and a shortage of these PMICs is impacting DDR5 shipments.

The growth can be attributed to the projected increase in mobile and other devices that use sophisticated power management techniques. For example, according to Hui He, an analyst at research firm Omdia, as reported by the Wall Street Journal, “a typical 5G smartphone can hold as many as eight power-management chips, compared with two to three in a 4G phone.”

“I have worked in the analog and power device sector for a long time and have witnessed firsthand the challenges to scaling these devices compared to digital,” said Lou Hutter, principal at Lou Hutter Consulting, in a statement. “Combining this ‘scaling gap’ with the increasing prevalence of these devices is certainly one of the factors behind industry shortages we see in these devices. Atomera’s MST-SP technology can significantly shrink the power transistors that routinely occupy 40% to 80% of the area in a PMIC, which enables manufacturers to get 20% more die per wafer — and with lower power consumption to boot.”

BCD technologies face more difficult scaling challenges than their digital counterparts and as a result have not seen the process node advances that digital chips have. While some market leaders have introduced advanced BCD processes at the 40nm nodes, most BCD devices are produced at older-generation process nodes.

MST-SP allows BCD PMIC manufacturers to get up to 20% more die per wafer, enabling manufacturers to improve the profitability of existing fabs and/or improve the return on their investments in new processes and capacity.

Atomera’s chief technology officer Robert Mears said in an interview that power-related chips are proliferating in everything from battery-operated devices to those with universal serial bus (USB) connectors. And keeping the costs manageable while hitting performance and power targets isn’t easy with the current state of affairs.

Above: There are a lot of power chips in iPhone 13 models.

Image Credit: Atomera

“The difference here is you’ve got one technology that improves both flavors of transistor,” Mears said. “And it’s also complementary and additive. It has an inherent mobility benefit, depending a little bit on which node you’re looking at.”

The quantum layer of film gives chip creators a unique ability to control the doping, or dropping of chemicals in a particular spot on the chip, across a wide range of applications, Mears said.

The challenge limiting the ability to transition BCD power devices to smaller manufacturing nodes has been sufficiently improving the on-resistance for a given breakdown voltage while ensuring reliability isn’t compromised. It is easy to lower the resistance of a device – but it will burn-out at a lower voltage. There is a tradeoff between on-resistance and ability to withstand higher voltages. Typically one targets an operating voltage and then tries to lower the on resistance just to the point where it operates at the voltage but not higher.

MST-SP provides two fundamental benefits.

IDlin is the current a transistor passes in the linear regime which is for a low voltage between source and drain.

One is on-state mobility, or higher Idlin, and the second is an ability to control the doping with a degree of precision that is not possible with other approaches. The doping benefits also translate into improvements in the breakdown voltage as well as the overall ability to scale the gate length lower without losing breakdown voltage. The net effect is a 20% improvement in Idlin for a given VDS max, a key reliability parameter for the lifetime of the device. (VDS is the source-drain voltage across the transistor).

The ability to scale the gate length while maintaining reliability also addresses the key challenge in moving BCD power devices to smaller nodes. By enabling a gate length shrink without compromising the reliability of the power device, manufacturers can take better advantage of a design rule shrink to reduce the overall device pitch. For 5V PMIC, this enables up to 20% more dies per wafer.

Above: The benefits of Atomera.

Image Credit: Atomera

MST-SP is available to license today for 5V power devices, which is the predominant operating voltage for BCD PMIC devices today. Atomera’s engineering team can customize MST-SP to both higher and lower voltages.

Before the company went public, it raised $83.4 million. And as a public company, it raised $80 million.

The solution is complementary and additive compared to other efforts chip makers are making, Lewis said. And in contrast to past licensors like Rambus, which got into legal troubles with chipmakers over licensing, Lewis said that the chip industry is free to license the technology or not.

Regarding performance, Mears said, “We haven’t seen anybody coming close to these numbers, as well as the smallest area and cost across different processes.”

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