Intel has demonstrated an eight-wavelength laser array on a silicon wafer. The research paves the way for the next generation of integrated silicon photonics products in the data center, such as switches with co-packaged optics and chiplets for optical interconnects.

From discrete transceivers to integrated photonics

Intel has been selling 100G transceivers based on silicon photonics for about half a decade, and has also started to commercialize up to 400G transceivers, with 800G also on the roadmap. Gartner forecasts that by 2025 over 20% of all data center communication will be based on silicon photonics, up from 5% in 2020, representing a $2.6 billion market. 

However, to further reduce power, the next step for silicon photonics is to become more tightly integrated with other silicon. The first instantiation of this is co-packaged optics, expected in the next two years. The ultimate goal is fully integrated photonics, where the photonic integrated circuit is directly connected to the rest of the compute using advanced packaging. 

Integrated DWDM laser array

The latest research from Intel Labs delivers what it calls “industry-leading” advancements in multiwavelength integrated optics, Intel claims. It concerns the demonstration of an eight-wavelength distributed feedback (DFB) laser array that was fully integrated on a 300mm silicon wafer using Intel’s hybrid silicon photonics platform, paving the way for cost-effective high-volume manufacturing for broad deployment. The laser achieved power uniformity and wavelength spacing uniformity that exceed industry specifications.

One of the differentiated features of Intel’s 300mm wafer silicon photonics platform is its integrated hybrid silicon laser. The new multiwavelength advancement enables the production of the optical source for future high-volume applications such as co-packaged optics or optical interconnects, facilitating the growing bandwidth requirements of data-intensive applications such as  artificial intelligence (AI) and machine learning (ML). 

More specifically, the laser uses a technology called dense wavelength division multiplexing (DWDM) in order to send different, closely spaced wavelengths over the same optical link. This technique thus increases the bandwidth while also reducing the physical size of the photonic chips. The key challenges that were overcome were the uniformity of the power and wavelength spacing. 

Intel’s current silicon photonics transceivers use coarse wavelength division multiplexing (CWDM) where the wavelengths are further apart. These products use 100G lines using four wavelengths that deliver 25G bandwidth each. 

To realize the eighth-wavelength DFB array, Intel used advanced lithography (the same technique that is used to define features on chips) to define the wavelength gratings in silicon prior to the III-V wafer bonding process where the III-V laser is attached to the silicon wafer. Intel said this resulted in better wavelength uniformity compared to conventional semiconductor lasers manufactured in 3-inch or 4-inch III-V wafer fabs. Due to the tight integration, this uniformity remained even in different ambient temperatures.

“This new research demonstrates that it’s possible to achieve well-matched output power with uniform and densely spaced wavelengths,” said Haisheng Rong, senior principal engineer at Intel Labs. ” Most importantly, this can be done using existing manufacturing and process controls in Intel’s fabs, thereby ensuring a clear path to volume production of the next-generation co-packaged optics and optical compute interconnect at scale.”

Optical chiplets

Intel said the integrated laser array from this research is being implemented by its Silicon Photonics Products Division. Intel is targeting a future optical compute interconnect chiplet product that will offer “multi-terabits per second” bandwidth between compute resources such as the CPU, GPU and memory. This fits into Intel’s longstanding vision that optical I/O will eventually complement or even replace existing copper-based interconnects such as PCIe, offering higher bandwidth and lower power.