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ARM is the most successful microprocessor architecture on the planet, with its licensees shipping billions of chips a year. But a rival has emerged in the past few years called RISC-V, a new kind of royalty-free architecture started by academics. Its proponents are holding an event in the heart of Silicon Valley to tout its growth.
This week, 2,000 engineers and other professionals are attending the RISC-V Summit in San Jose, California. The leaders of RISC-V made their case that the architecture — which enables members to design processors and other chips that are compatible with software designed for it — is moving well beyond its academic roots.
Cambridge, England-based Arm has been around for decades, and its designs are used in everything from smartphones to servers. Its customers have shipped more than 150 billion chips to date, and the pace is accelerating — the company is targeting 50 billion chips in the next two years. But some chip companies — and startups like SiFive — want more design freedom and lower license costs than Arm can provide.
RISC-V started in 2010 at the University of California at Berkeley Par Lab Project, which needed an instruction set architecture that was simple, efficient, and extensible and had no constraints on sharing with others. So Krste Asanovic (a founder of SiFive), Andrew Waterman, Yunsup Lee, and David Patterson created RISC-V. They built their first chip in 2011. In 2014, they announced it and gave it to the community.
In an interview, Patterson (a former UC Berkeley computer science professor and current Google distinguished engineer) said the original motivation was to experiment more with chip design because Moore’s Law, the prediction that the number of transistors on a chip doubles every couple of years, was slowing down. If manufacturing advances could no longer deliver gains in chip productivity, chip designers would have to step up and deliver better results with clever chip designs that yield better chip performance, Patterson said.
The academic group was inspired by what Linux had achieved with open source software. But there was no equivalent in open source hardware. When the academics found they couldn’t get inexpensive licenses to proceed with their research, they decided to make their own architecture — the framework for whole families and generations of processors. They wanted to do for hardware what Linux did for software.
“This is what has happened in software. There are open and proprietary versions. There were times when people thought proprietary software was a monopoly,” said Patterson. “We had no choice. We had to use that. I think it’s healthy to have both. And it also puts kind of pressure on the proprietary competition. If there isn’t an alternative for them, then that probably stifles innovation, and it’s bad for the people in the ecosystem. So I think it’s healthier for the customers and probably healthier for the companies to have competition.”
Patterson was a legendary figure in the microprocessor wars of the 1980s and 1990s. He was a co-inventor of RISC (reduced instruction set computing) and argued against CISC (complex instruction set computing). Companies like Arm, Sun Microsystems, and Mips (started by Patterson’s computer science textbook co-author and former Stanford University president John Hennessey) espoused RISC, while Intel focused on CISC. While Intel won the PC wars, RISC remains the winner thanks to Arm’s dominance in smartphones.
Now Patterson and his fellow Berkeley academics are engaged in a battle to unseat Arm.
“We were always jealous in universities that you could get industrial-strength software that was open,” Patterson said. “But when it came to hardware, it was proprietary. Now, with RISC-V, we get the same kind of benefit. It helps educationally, and it helps competition.”
Although they toyed with the idea for decades, the upstarts finally started the RISC-V Foundation as an independent nonprofit in 2015. It’s not an open source processor. It’s an open specification, and because it is open, members can create their own open source cores for processors.
In 2016, Nvidia announced it would use RISC-V as a controller in its graphics processing units (GPUs). Nvidia is now shipping millions of those chips. That said, in such chips RISC-V likely handles smaller tasks as an embedded control processor, while the device still uses an ARM design as a main processor. In 2017, Western Digital said it would move its entire product line to RISC-V, and it has open-sourced its cores. Last year, the group had its first summit, and this week the second summit is happening.
“The original specs have now been ratified, and here we are at the second summit,” Asanovic said in a keynote address. “It’s not because it’s 10% faster. It’s because it’s a new business model.”
In the old days, chip designers had to pick the vendor to make their chip. With RISC-V, you can select it and then “all of the vendors compete for your business,” Asanovic said. “You can add your own extensions without getting permission.”
In addition, chip juggernauts like Intel are finding it hard to maintain the pace of Moore’s Law through manufacturing advances alone. That is putting more pressure on designers to create application-specific processors to make up for the slowdown, Patterson said. But instruction-set owners such as Arm aren’t motivated to allow such customization because it can lead to fragmentation. Arm only recently moved to allow customization this year, long after RISC-V debuted.
Semico Research estimated that there will be 62.4 billion RISC-V cores shipping in 2025. It’s not just for microcontrollers, Asanovic said. There is demand for every performance level.
“Success is great, and it’s a great problem to have,” he said. “The ISA foundation is in place. This is basically taking over the industry.”
What Arm thinks
Arm is not impressed. “Arm represents more than just an instruction set architecture,” an Arm spokesperson told VentureBeat. “Arm offers a roadmap of products, supporting a broad range of applications and a proven track record of successfully enabling our partners to address the long-term needs of the market. Arm’s shared success model, combined with the world’s largest and open compute ecosystem of tools, services, and software, has resulted in our partners shipping more than 150 billion ARM-based chips to date on a path toward a trillion connected devices by 2035.”
In October, I asked Arm CEO Simon Segars about RISC-V in an interview during Arm’s conference in the same convention center. At that time, Segars had just announced custom instructions, which seemed like a nod in the direction of the flexibility offered by RISC-V. He said the following:
The way we’re looking at it is that chip design is evolving in multiple ways in parallel. You have consolidation going on amongst big chip companies, producing large players who are investing on the leading edge. They have the size and scale to build very complex devices. You have some OEMs who want to build chips. You have various smaller companies who are looking at how to create things much more optimized for specific applications, especially in this world of IoT. There’s a range of different solutions out there for how people can extend the capability of what an ARM processor does based on the workload.
Our inclusion of the custom instructions is based on feedback from the market. In some areas, having a dedicated accelerator sitting in the memory map or sitting as a co-processor, that works very well. There are some other applications where doing that final optimization can make a big difference. We’ve listened to the market. We’ve thought long and hard about how we add that flexibility and maintain the benefits we’ve had for our entire history of standardization and that big software ecosystem we’ve developed. This seems like a good way to address all those needs. It’s really driven by the needs of the market more than anything else.
The RISC-V Foundation’s leaders talked about being an alternative, but they also acknowledged that the competition with Arm isn’t as severe as it might seem. After all, many chips could have smaller RISC-V control processors coupled with ARM main processors, said Alessandro Piovaccari, chief technology officer of Silicon Labs, in an interview with VentureBeat.
“Arm is not our role model,” Asanovic said. “I would say that would be a disappointing ambition. It’s a much bigger deal than replacing one company.”
Patterson added, “That would be like saying we’re going after Intel. Our high-end things will probably compete in the cloud with x86 in the cloud. But we’re not trying to destroy either company.”
The RISC-V Foundation’s rapid growth
But if there is an opportunity, it’s in new markets for semiconductors, such as the burgeoning internet of things (IoT).
“You’ll see how many members have joined this revolution, and it’s a revolution,” said Calista Redmond, CEO of RISC-V Foundation, in an opening talk at the summit. “I’m signing about two membership agreements a day. In China, we are seeing hundreds joining. Welcome to the revolution. There has never been a better time to design a microprocessor.”
Redmond said the group now has 435 companies in the RISC-V Foundation — 44 of those are chip companies, nine are input-output companies, 32 are research groups at universities, 25 are software companies, 31 are services firms, and the rest are from various industries. Commercial tool providers are supporting the group. In an interview with VentureBeat, Redmond said such growth hasn’t happened with other architectures in years.
And board members predict the group will grow its membership by 50% in 2020. By 2021, a billion cores are expected to ship using the RISC-V architecture, said Zvonimir Bandic, a foundation board member and senior tech director at Western Digital.
Europe and India have also hosted conferences. The Shakti Project in India has funded six processor design projects. And RISC-V has been designated the National Architecture of India and Pakistan. In Pakistan, a gathering drew 3,000 people. Meetups have drawn more than 2,000 people.
An event in Tokyo drew 360 registered attendees. In North America, companies shipping millions of cores include Nvidia, Western Digital, and SiFive. The foundation has the first version of its compliance framework ready, and it has working groups on security, safety, and other matters.
Concerns about China and trade barriers
China is one of the faster-growing markets, Asanovic said. In an interview, he said that RISC-V saw a burst of activity in China following controversy that forced Arm to decide whether to sever relations with China’s Huawei after the U.S. implemented a trade ban over national security concerns. Ultimately, Arm decided it could continue to license its chip architectures to Huawei, as the technology originated in the United Kingdom, and not the U.S. The ban blocks U.S. companies from working with Huawei.
But there are no such concerns with the open source hardware that is the basis for RISC-V, Redmond said. Patterson said the CEO of Infineon once asked him if RISC-V technology could be blocked as a result of a hypothetical trade dispute. Because such concerns arose, the RISC-V Foundation is in the midst of moving its legal headquarters to Switzerland, which is considered a neutral territory. That helps remove any perception that RISC-V is a U.S.-based nonprofit. All of this concern about trade disputes has drawn a lot of attention to RISC-V, Asanovic said.
Martin Fink, adviser to the CEO at Western Digital, said, “When we saw RISC-V, we saw an opportunity to accomplish things that would not be possible with other solutions in the market.” He said Western Digital’s end goal was to unshackle main memory from its processor. He said that Western Digital believed processors do not have to be directly connected to main memory chips.
It took Western Digital a few years to design its solution for a core using RISC-V. The company launched the Swerv core a year ago and open-sourced it.
“Before I joined Western Digital, I hadn’t heard of RISC-V,” he said. “I was frustrated with the same things. All of the interfaces associated with the processor were locked down. In 2017, we went all in. We are currently delivering a billion cores a year in our products, and we expect all of those to be RISC-V.”
Ted Speers, head of architecture and planning at Microchip, said he first heard about RISC-V during a meeting in December 2014. He became a convert and convinced a colleague to believe in it. He said in five years RISC-V has provided an architectural alternative to innovate as Moore’s Law slows down. He also noted that there is a pipeline of talent coming into RISC-V through universities, and venture capital for RISC-V startups is starting to pour in, as well.
Microchip created an SoC FPGA dubbed PolarFire SoC with a hardened real-time, Linux capable, RISC-V-based microprocessor subsystem. Speers said RISC-V is “making hardware cool again” and added, “We are all excited because we know we are part of something big.”
Junho Huh, research vice president at Samsung Electronics, said the company has designed RISC-V into its Exynos and Isocell chips so far. Previous Exynos modem chips have shipped in more than 600 million devices to date. It was a risk to use RISC-V, but the company expects to introduce RISC-V across a large number of products in the future, including AI, security, and safety chips, Huh said. Sure, it’s just a research executive saying that. But over time, that could result in a lot of new chips.
This potential has Redmond smiling. As she says, “The new chips are where the growth is in the market.”
SiFive has the widest family of RISC-V cores on the market and has been evangelizing them around the world. Yunsup Lee, chief technology officer of SiFive, said he was struck by the concept at a SiFive symposium in Pakistan, where a student had printed out a copy of the first thesis written on RISC-V by Waterman. SiFive is moving into consumer IoT, deep learning, industrial IoT, and other markets.
Lee said, “We are changing the world. RISC-V has already changed it. Hardware is cool again for students.”
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