AI models shift in months, but the chips they run on are locked in years earlier. Researchers at one startup say AI itself can shrink that cycle to weeks by running the entire design flow, from a written spec to a working FPGA implementation.

In a paper published in August, startup Architect Labs describes how its AI system, the Architect Labs Platform, designed a small, low-power inference chip, dubbed Redwood, from a written spec, with no human intervention below the specification. In their experiments, two human architects wrote a high-level chip specification; the system then handled performance modeling, generated the digital hardware descriptions, tested and verified the design, and produced the firmware and kernels.

This process took under two weeks, according to the researchers. Once specification changes were verified, a modified design was back on the FPGA in less than 48 hours. In a conventional flow, the researchers note, design stages are frozen as they go, and changes are either made ad hoc or held for the next generation.

The key question going forward, though, is whether this demonstration can translate into fabricated silicon: The performance advantage over Nvidia is based on projections, calibrated against the FPGA results, for an as-yet-unbuilt Samsung 8nm-class implementation. Next, the researchers plan to scale Redwood to larger models and fabrics and move into physical design, tapeout and post-silicon validation.

If the design holds up in fabricated silicon, the bigger consequence may be less about Redwood itself than about the design cycle: Hardware teams could iterate around fast-changing AI workloads instead of committing years in advance to assumptions about what future models will need.

“We argue that the opportunity for AI in hardware design is not task acceleration within the existing flows but the reimagining of the entire flow itself,” the Architect Labs researchers write. 

How AI runs the whole chip design flow

Just 14% of integrated circuit (IC) and application-specific integrated circuit (ASIC) projects achieved first-silicon success in 2024, the lowest rate in two decades. And 75% of projects ran behind schedule, according to a functional verification study Siemens EDA commissioned from Wilson Research Group.

As a result, chip design decisions are "committed under deep uncertainty and paid for twice," the Architect Labs researchers write — "once in the generality added as a hedge, and again when new workloads map poorly onto frozen silicon."

AI-generated hardware projects to date have also been limited to simple or small-scale components, the researchers note.

Architect Labs says its Redwood AI accelerator was designed, verified, programmed, and deployed end to end from scratch by an AI system. According to the researchers, every block reached 95% code and functional coverage without human verification engineers participating. The researchers report that no bugs were found in the first RTL design sent from simulation to the field-programmable gate array (FPGA), and that moving optimization runs onto the FPGA reduced them from 15 hours to 15 to 30 minutes.

The system can explore a microarchitectural search space an order of magnitude larger than a human team can cover in the same time, according to the researchers. For one vector engine, it generated and verified multiple design options with varying control logic and data paths, working over several days to optimize for area and timing constraints.

Human experts adjust the specification using functional, area, performance, timing and power feedback, and the system regenerates and reverifies the design from there, the researchers explain. The software-to-silicon stack is collapsed into a “single optimization loop, where hardware and software are co-designed and verified under one objective.” 

How Redwood is built

Redwood is designed to address three practical problems: latency, power, and predictability. 

Data is kept as close to compute units as possible to reduce the need to shuttle it back and forth. The chip features a grid of identical building blocks (“tiles”). Each performs a specific slice of work and passes it to neighboring tiles. Data flows in a planned pattern rather than being repeatedly (and unnecessarily) pulled from shared memory. 

Redwood conserves power by separating control from compute; logic can slow down or power off. Near-memory compute and flow control on the on-chip network cut energy wasted on moving data. And a global timer that schedules each kernel makes the process more predictable. 

Measured on an FPGA, projected on silicon

In performance analysis, the researchers evaluated a specific configuration they called Redwood Nano, an FPGA variant of the design, running it against Nvidia’s Jetson Orin Nano, which the researchers use as the commercial baseline for edge AI.

In measured results, Redwood Nano, running on the FPGA, achieved an average throughput of 12.1 tokens per second when running at 250 megahertz on the Qwen3 0.6B large language model (LLM). By contrast, Jetson Orin Nano, running at a clock speed of 1020 megahertz, achieved an average throughput of 28 tokens per second. 

The advantage over Nvidia shows up only in the researchers’ estimates for fabricated silicon. Using a Samsung 8nm-class process comparable to the one used by Nvidia’s Jetson Orin Nano, they project Redwood Nano would reach 49 tokens per second — 1.75X the Jetson’s measured throughput — while drawing roughly half the power (1.335 watts vs. 2.59), for a 3.4X improvement in performance per watt. They estimate its NPU block would occupy just 2.88 square millimeters.

The researchers characterize another experiment as an early form of recursive self-improvement, though it is far narrower than the autonomous, self-improving models the term usually refers to. They deployed Qwen3 on Redwood, exposed it as an inference endpoint within their AI system and sampled it repeatedly. The model found multiple timing improvements and kernel optimizations for several of its own operations.

“We believe this is one of the earliest demonstrations of recursive self-improvement: an AI system designed an AI accelerator, deployed an AI model on it, and used that model to improve a future generation of the accelerator,” the researchers write. In a blog post, Architect Labs says it is working toward a tapeout of Redwood at TSMC.